1. Field of the Invention
The present invention relates to memory devices based on multi-level cells (“MLCs”), and more particularly to techniques for programming and reading MLC-based memory devices.
2. Description of Related Art
Conventional flash memory cells store charge on a floating gate. The stored charge changes the threshold voltage (Vth) of the memory cell. In a read operation, a read voltage is applied to the gate of the memory cell, and current through the cell indicates the programming state of the memory cell. For example, memory cell that conducts a first current value during a read operation might be assigned a digital value of “1”, and a memory cell that conducts a first current value during a read operation might be assigned a digital value of “0”. Charge is added to and removed from the floating gate to program and erase the memory cell, i.e., to change the stored value from 1 to 0. The charge is retained by the floating gate until the memory cell is erased, retaining the data state without continuously applied electrical power.
FIG. 1A shows a memory cell distribution versus threshold voltage Vth for a conventional memory array. Memory cells in a low Vt state have threshold voltages within a first range 102 and memory cells in a high Vt state have threshold voltages within a second range 100. A cell can be determined to fall within a low threshold range by measuring whether the threshold of the cell is lower than the maximum threshold for the range, where the maximum threshold can be defined as an erase verify EV level, A cell can be determined to fall within a high threshold range by measuring whether the threshold of the cell is higher than the minimum threshold for the range, where the minimum threshold can be defined as a program verify PV level. In practice the erase verify voltage may be slightly higher than the maximum of the range, and the program verify voltage may be slightly lower than the minimum of the range. In a conventional single-level cell (“SLC”) memory, the read window WL used to distinguish low Vt cells in range 102 from high Vt cells in range 100 is the difference between a program-verify PV level and an erase-verify EV level. The distribution of unprogrammed, unerased SLCs VtINIT can be different than the programmed or erased distributions as shown in a dashed line.
MLCs have been developed that can indicate (store) multiple data values by providing selectively different amounts of charge on the floating gate. MLCs increase the amount of data that can be stored on the same area of an IC compared to an SLC, increasing memory density. Basically, a little bit of negative charge slightly increases Vth of an MLC, and more negative charge further increases Vth. A read operation is used to determine what state the memory cell has been charged (programmed) to.
FIG. 1B shows a memory cell distribution versus Vth for an MLC memory array. The MLC has four levels, L0, which is the erased condition, and programming levels L1, L2, and L3, which are levels where increasing amounts of negative charge have been transferred to the charge trapping structures of the MLCs, increasing Vth for each successive programming level. The read windows WL0-1, WL1-2, WL2-3 between levels depends on the Vth distribution of each programming level. In the MLC implementation, the data value corresponding to each of the four levels is a design choice. That is L0 to level L3 can map to (11, 01, 10, 00), (11, 01, 00, 10) or (11, 10, 00, 01), or others. Of course, to improve bit error count, a mapping like (11, 01, 00, 10) that results “just-one-bit-error while read shift one level” is often better.
Memory arrays incorporating MLCs are typically read in the well-known fashion of applying a read voltage (Vt) to a selected wordline, and comparing a voltage or current on the bitlines of a set of MLCs activated by the wordline to a reference. The reference is often produced using a reference cell having a selected thereshold voltage generally between the maximum Vth of a first programming level and the minim Vth of a second programming level. For example, the reference cell provides a reference current (IREF) to a sense amplifier that compares the current from the MLC (IMLC) to the current from the reference cell. If IMLC is higher than IREF, then the sense amplifier provides a first output, and if IMLC is lower than IREF, the sense amplifier provides a second output.
A typical read operation is page-based. For example, a two giga-bit (“2 Gb”) memory device (or memory array in an IC) can be configured in 128,000 two-kilobyte (“2 KB”) pages. An entire page may contain too many MLCs to simultaneously program because of device current limitations. Thus, a page can be further subdivided into “chunks” for programming, erasing and reading. A chunk is a convenient portion of a page for programming or other operations. For example, a 2 KB page can be subdivided into 16 chunks, each chunk having 128 Bytes.
FIG. 2 is a diagram of a system 200 illustrating a conventional program and read sequence. A user enters a program pattern 202 through an input buffer 204 into an SRAM buffer 206. The data from a chunk in the SRAM is programmed into a slot within a page 211 of an MLC memory array 212. After programming, a program verify operation is performed by reading the programmed values back 214 using a data transfer block 216 (e.g. sense amplifier array). A representative embodiment includes 64 sense amplifiers which are operated in parallel on a 64 cell block of data for the verify operation. For cells storing two bits of data, the 64 sense amplifiers are used for each of the four Vth distributions. The program verify results can be used to update the data in the SRAM buffer 206. If the read results match the program pattern in the SRAM, then the data is cleared. If the results do not match, then the data for un-matching bits remains set. If any bits remain set after the chuck has been programmed, then another programming pulse is applied to the MLCs using the data remaining in the SRAM, until successful programming is achieved for all four Vth levels, or a maximum number of retries.
The process is repeated until the whole chunk is programmed, and then repeated for each chunk until the whole page is programmed. Several other sequences are possible, but generally a chunk is programmed to the desired levels (see FIG. 1B, L1, L2, L3) and verified to confirm that the MLCs provide those desired levels when read. This is done for each chunk until the entire page passes program-verify.
During a read operation, the user obtains the page content by reading 214 the data stored in the MLC memory array 212. The results are written into the SRAM buffer 206, 64 cell block by 64 cell block until an entire chunk is read. The page data is delivered to an output buffer 218, and then the output data 220 is delivered to the user.
As the size of memory arrays increases, the process and operating variations across the array and across a page within an array increase as well, which in turn increase the width of Vth distributions. Wider Vth distributions reduce the margins between the levels for a given voltage headroom. It is desirable to provide a large margin between the Vth distributions for the multiple levels in a MLC in order to improve the reliability and speed of the reading and programming operations.